Masterclock TCDS Series Dokumentacja Pobierz pdf (Strona 6)

AD1974 Data Sheet

Rev. D | Page 6 of 24

Parameter Condition Comments Min Max Unit

PLL

Lock Time MCLK and LRCLK input 10 ms

256 f

VCO Clock 40 60 %

Output Duty Cycle

MCLK_O Pin

SPI PORT See Figure 5

CCH

CCLK high 35 ns

CCL

CCLK low 35 ns

CCLK

CCLK frequency f

CCLK

= 1/t

CCP

; only t

CCP

shown in Figure 5

10 MHz

CDS

CDATA setup To CCLK rising 10 ns

CDH

CDATA hold From CCLK rising 10 ns

CLS

Setup To CCLK rising 10 ns

CLH

Hold From CCLK rising 10 ns

CLHIGH

High Not shown in Figure 5 10 ns

COE

COUT enable From CCLK falling 30 ns

COD

COUT delay From CCLK falling 30 ns

COH

COUT hold From CCLK falling, not shown in Figure 5 30 ns

COTS

COUT tristate From CCLK falling 30 ns

ADC SERIAL PORT See Figure 13

ABH

ABCLK high Slave mode 10 ns

ABL

ABCLK low Slave mode 10 ns

ALS

ALRCLK setup

To ABCLK rising, slave mode

ALH

ALRCLK hold From ABCLK rising, slave mode 5 ns

ALS

ALRCLK skew From ABCLK falling, master mode −8 +8 ns

ABDD

ASDATA delay From ABCLK falling 18 ns

AUXILIARY INTERFACE See Figure 12

XDS

AAUXDATA setup To AUXBCLK rising 10 ns

XDH

AAUXDATA hold From AUXBCLK rising 5 ns

XBH

AUXBCLK high 10 ns

XBL

AUXBCLK low 10 ns

XLS

AUXLRCLK setup

To AUXBCLK rising

XLH

AUXLRCLK hold From AUXBCLK rising 5 ns

1 2 3 4 5 6 7 8 9 10 11 ... 23 24

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Masterclock TCDS Series Dokumentacja Strona 6

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